Dinesh Annayya
Dinesh Annayya
Head of Silicon Engineering
- Dinesh brings 25+ years expertise in Complex ASIC Design, Verification, DFT and Timing Closure. He has extensive hands-on experience in 180nm to 10nm tape-out related Timing closure/DFT. He was Domain knowledge on Computer Architecture/ Telecom/ Optical/ Networking area.
- Dinesh leads the System Engineering at BigEndian and co-leads the Engineering Leadership Council.
- Prior to BigEndian, Dinesh held senior positions at Cypress Semi, Centillium, Transwitch, Yagna Innovation and Intel. He holds 2 US patents in high-speed networking.
- Dinesh has a Master's in Industrial Electronics from NIT, Karnataka and B.E in Electronics from BIET, Davanegere. He is a passionate open-source EDA enthusiast who has submitted more than 20 open-source-based tape-outs. He is one of the few to showcase working silicon using an open-source tool flow.
- Life credo: “Embrace the value of lifelong learning. Stay curious and open to new knowledge”.